Low Power Multiplier Design with Improved Column Bypassing Scheme

Power, speed and area are prime design constraints for portable electronics devices and signal processing applications. Multiplier plays an important role in DSP applications. In this paper, a low power and high speed multiplier with improved column bypassing scheme is presented. Primary power reduction is obtained by disabling the supply voltage of non-functional blocks when the operands of the multiplicands are zero. Power reduction is achieved by both architecture and circuit level modifications. The proposed multiplier consists of new adder architecture which is also responsible for reducing the power consumption and propagation delay. Simulation results are obtained with UMC 90nm and 0.9 V CMOS technology with cadence spectre simulation tool. The proposed multiplier has been compared with popular multipliers and performance parameters in terms of power dissipation, speed and area occupation are found better. The proposed multiplier is definitely a better choice for low frequency (≤ 50 MHz) applications. The results are obtained for randomly generated input test patterns having uniform distribution probability and more power can be saved if operands have more 0’s than 1’s.